This invention relates generally to integrated circuit memories and more particularly integrated circuit memories having standby/power enable circuitry.
As is known in the art, integrated circuit memories have a wide range of applications. In some applications, as in so-called non-volatile memories where power is not required to retain stored data as in a read-only memory (ROM) or programmable read-only memory (PROM), decoupling of a power supply from the addressing circuitry of such memories during a standby mode is sometimes provided. In one type of bipolar PROM/ROM circuit, addressing signals are fed to the addressing circuit which includes two sections: An inverter/buffer section which, in response to the addressing signals, produces "true" and "complementary" signals for each one of the bits of the addressing signal fed to the addressing section; and a decoder section which, in response to the "true" and "complementary" signals, addresses one of a plurality of conductors of the memory array to which a row of memory elements is coupled. In one such type of bipolar ROM/PROM circuit the decoder section includes Schottky transistor-transistor-logic (TTL) gates and prior to enabling of such gates, that is prior to electrically coupling of such gates to a power source (as when the memory circuit is in the standby mode), the output of such gates, and hence the voltages on the rows of conductors, are a "high" voltage relative to the substrate on which such conductors are disposed. The plurality of conductors together with the substrate thus provide a capacitor. In order for the decoder to respond to the addressing signals once the memory is placed in the enable mode, that is once it is coupled to the power source, it is necessary to rapidly discharge the voltages on the conductors to ground and thereby reduce the effect of the capacitance on the delay, or the response time, of the memory to the enable signal.